1. Field of the Invention
The present invention generally relates to a watchdog timer that is embedded in a microcomputer incorporated into electronic equipment to reset the microcomputer if it runs away, and particularly to a watchdog timer that can reset the microcomputer before it runs away by detecting a narrow operation margin state such as a low supply voltage and a high operation frequency, thereby ensuring the safety of the system incorporating the microcomputer.
2. Description of Related Art
Recently, various types of circuits are embedded into microcomputer chips as a countermeasure against runaway of microcomputers incorporated into electronic equipment. A watchdog timer, one of such circuits, has a function to detect the microcomputer chip running away, and to reset the microcomputer.
FIG. 11 is a block diagram showing a configuration of a conventional watchdog timer. In this figure, the reference numeral 1 designates a counter that receives a clock xcfx861 as a count source, and outputs an overflow signal when its count reaches a predetermined number. The overflow signal is supplied to a system reset terminal (not shown) as a reset signal of the microcomputer.
The reference numeral 3 designates an instruction decoder that sequentially decodes instructions and outputs decoded results 5. When decoding a watchdog timer initialization instruction, the decoder 3 imposes an instruction pulse on a signal line WDC. The instruction pulse on the signal line WDC is supplied to the counter 1 as an initializing signal for initializing the count of the counter 1. The counter 1, receiving the instruction pulse via the signal line WDC, initializes its count. When producing software, the watchdog timer initialization instruction is inserted into a software loop at such intervals that can prevent the overflow of the counter 1. This can prevent, as long as the microcomputer operates normally, the reset signal from being output from the counter 1 because the instruction decoder 3 regularly supplies the instruction pulse to the counter 1 and hence the count of the counter 1 is initialized regularly.
However, if the microcomputer runs away because of a narrow operation margin state such as a low supply voltage or a high operation frequency, or because of incoming noise, it cannot execute the software loop normally, thereby hampering regular generation of the instruction pulse, disabling the regular initialization of the count of the counter 1. As a result, the counter 1 overflows, generates the reset signal, and supplies it to the system reset terminal (not shown), thus resetting the microcomputer.
With the foregoing configuration, the conventional watchdog timer cannot reset the microcomputer before it runs away. This presents a problem of being unable to ensure the safety of the system, into which the microcomputer is incorporated, because an unexpected signal can be output from a port of the microcomputer in the interval between the runaway of the microcomputer and the actual reset of the microcomputer, during which the overflow of the count of the counter 1 and the supply of the reset signal to the system reset terminal take place. Thus, the conventional watchdog timer has a problem of being unable to secure the safety of the system because it cannot detect the low voltage state or incoming noise, and hence cannot reset the microcomputer until the microcomputer actually runs away.
The present invention is implemented to solve the foregoing problems. It is therefore an object of the present invention to provide a watchdog timer capable of implementing the safety of the system into which the microcomputer is incorporated by resetting the microcomputer before it runs away, that is, during its normal operation, by detecting the occurrence of a narrow operation margin state such as a low supply voltage and a high operation frequency, in addition to the function of the conventional watchdog timer to detect the runaway of the microcomputer and reset it.
According to a first aspect of the present invention, there is provided a watchdog timer comprising: a counter for counting a first clock, and for outputting, when its count reaches a predetermined number, a reset signal for resetting operation of a microcomputer; an instruction decoder for decoding a watchdog timer initialization instruction regularly executed, and for outputting a first pulse signal used for initializing the count of the counter; and a delay circuit for delaying a rising edge of the first pulse signal, and for supplying the counter with the delayed first pulse signal as an initializing signal of the count, wherein the delay circuit prevents the first pulse signal from being supplied to the counter if at least one of two cases takes place in which an operation frequency of the microcomputer is higher than a predetermined frequency, and a supply voltage to the microcomputer is lower than a predetermined value.
According to a second aspect of the present invention, there is provided a watchdog timer comprising: a counter for counting a first clock, and for outputting, when its count reaches a predetermined number, a reset signal for resetting operation of a microcomputer; an instruction decoder for decoding a watchdog timer initialization instruction regularly executed, and for generating a first pulse signal used for initializing the count of the counter; and a delay circuit for delaying a rising edge of a second clock having a same timing as the first pulse signal output from the instruction decoder, and for outputting as a second pulse signal the second clock with its rising edge delayed by a predetermined time period, wherein the delay circuit prevents the second pulse signal from being output if at least one of two cases takes place in which an operation frequency of the microcomputer is higher than a predetermined frequency, and a supply voltage to the microcomputer is lower than a predetermined value; and an AND circuit for performing an AND operation between the first pulse signal supplied from the instruction decoder and the second pulse signal supplied from the delay circuit, and for supplying a result of the AND operation to the counter as an initializing signal of the count.
Here, the watchdog timer may further comprise: an n-bit shift register for successively loading a logical high level in response to the second clock, and for initializing, in response to the second pulse signal supplied from the delay circuit, all bits of then-bit shift register simultaneously to a logical low level; and an NAND circuit for carrying out an NAND operation between all the bits of the n-bit shift register, and supplies its operation result to the AND circuit, wherein the n-bit shift register and the NAND circuit are interposed between the delay circuit and the AND circuit.
The watchdog timer may further comprise a CPU for discriminating the operation result of the NAND circuit using software.
The CPU may make a decision of the operation result output from the NAND circuit, and generate an interrupt in response to the decision of the operation result before a reset signal is output by an overflow of the count of the counter.
The delay circuit may comprise: an even number of inverters connected in series; a plurality of load capacitors connected between a ground and nodes between adjacent inverters; and an AND circuit for performing an AND operation between a signal input to an initial stage inverter and a signal output from a final stage inverter of the even number inverters.
The delay circuit may comprise: an even number of inverters connected in series; a plurality of load capacitors connected between a ground and nodes between adjacent inverters; an AND circuit for performing an AND operation between a signal input to an initial stage inverter and a signal output from a final stage inverter of the even number inverters; a register for storing a set value for determining a value of the load capacitors in the delay circuit; and a first selector for adjusting the value of the load capacitors in the delay circuit in response to the set value placed in the register.
The delay circuit may comprise: an even number of inverters connected in series; a plurality of load capacitors connected between a ground and nodes between adjacent inverters; an AND circuit for performing an AND operation between a signal input to an initial stage inverter and a signal output from a final stage inverter of the even number inverters; a register for storing a set value for determining a number of stages of the even number inverters in the delay circuit; and a second selector for selecting the number of stages of the even number inverters in the delay circuit in response to the set value placed in the register.
The delay circuit may comprise: an even number of inverters connected in series; a plurality of load capacitors connected between a ground and nodes between adjacent inverters; an AND circuit for performing an AND operation between a signal input to an initial stage inverter and a signal output from a final stage inverter of the even number inverters; a register for storing a set value for determining a value of the load capacitors and a number of stages of the even number inverters in the delay circuit; and a second selector for selecting the value of the load capacitors and the number of stages of the even number inverters in the delay circuit in response to the set value placed in the register.
According to a third aspect of the present invention, there is provided a watchdog timer comprising: a counter for counting a first clock, and for outputting, when its count reaches a predetermined number, a reset signal for resetting operation of a microcomputer; an instruction decoder for decoding a watchdog timer initialization instruction regularly executed, and for generating a first pulse signal used for initializing the count of the counter; a supply voltage detector for detecting a level of a supply voltage to the microcomputer, and for outputting a high-level signal when the level of the supply voltage is greater than a predetermined level; and an AND circuit for performing an AND operation between the first pulse signal supplied from the instruction decoder and the high-level signal supplied from the supply voltage detector, and for supplying a result of the AND operation to the counter as an initializing signal of the count.